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Design Rule

1.IC Test Substrate

FEATURE
□ High pin counts
□ BUx10+COREx16+ BUx10 Layer counts max.
□ Total Max. Thickness 4.0mm

2.IC Packaging Substrate

FEATURE
□ Bump counts
□ Max. Bux9+COREx2+ Bux9 Layer counts
□ Total Max. Thickness 3.6mm